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CY7C225A
512 x 8 Registered PROM
Features
* CMOS for optimum speed/power * High speed -- 25 ns address set-up -- 12 ns clock to output * Low power -- 495 mW (Commercial) -- 660 mW (Military) Synchronous and asynchronous output enables On-chip edge-triggered registers Buffered common PRESET and CLEAR inputs EPROM technology, 100% programmable Slim 300-mil, 24-pin plastic or hermetic DIP, 28-pin LCC, or 28-pin PLCC * 5V 10% VCC, commercial and military * TTL-compatible I/O * * * * * * Direct replacement for bipolar PROMs * Capable of withstanding greater than 2001V static discharge
Functional Description
The CY7C225A is a high-performance 512-word by 8-bit electrically programmable read only memory packaged in a slim 300-mil plastic or hermetic DIP, 28-pin leadless chip carrier, and 28-pin PLCC. The memory cells utilize proven EPROM floating gate technology and byte-wide intelligent programming algorithms. The CY7C225A replaces bipolar devices and offers the advantages of lower power, superior performance, and high programming yield. The EPROM cell requires only 12.5V for the supervoltage and low current requirements allow for gang programming. The EPROM cells allow for each memory location to be tested 100%, as each location is written into, erased, and repeatedly exercised prior to encapsulation. Each PROM is also tested for AC performance to guarantee that after customer programming the product will meet AC specification limits.
Logic Block Diagram
A0 A1 A2 A3 A4 A5 A6 A7 A8 COLUMN ADDRESS O2 O1 ADDRESS DECODER 8-BIT EDGETRIGGERED REGISTER ROW ADDRESS PROGRAMMABLE ARRAY MULTIPLEXER O5 O4 O7
Pin Configurations
DIP Top View
A7 O6 A6 A5 A4 A3 A2 A1 A0 O3 O0 O1 O2 GND 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VCC A8 PS E CLR ES CP O7 O6 O5 O4 O3
CLR CP A4 A3 A2 A1 A0 NC O0
ES E
4 3 2 1 28 27 26 25 5 24 6 23 7 22 8 21 9 20 10 19 11 12 13 141516 17 18 O1 O2 GND NC O3 O4 O5
A5 A6 A7 NC VCC A8 PS E CLR ES CP NC O7 O6
PS
S
R
CP
O0
LCC/PLCC Top View
Cypress Semiconductor Corporation Document #: 38-04001 Rev. *C
*
198 Champion Court
*
San Jose, CA 95134-1709 * 408-943-2600 Revised August 16, 2006
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CY7C225A
Selection Guide
7C225A-25 Minimum Address Set-Up Time Maximum Clock to Output Maximum Operating Current Commercial Military 25 12 90 7C225A-30 30 15 90 120 7C225A-40 40 25 Unit ns ns mA mA
Maximum Ratings[1]
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ..................................... -65C to +150C Ambient Temperature with Power Applied.................................................. -55C to +125C Supply Voltage to Ground Potential (Pin 24 to Pin 12).................................................-0.5V to +7.0V DC Voltage Applied to Outputs in High Z State .....................................................-0.5V to +7.0V DC Input Voltage .................................................-3.0V to +7.0V
DC Program Voltage (Pins 7, 18, 20) ........................... 13.0V Static Discharge Voltage............................................ >2001V (per MIL-STD-883, Method 3015) Latch-Up Current ..................................................... >200 mA
Operating Range
Range Commercial Military[2] Ambient Temperature 0C to +70C -55C to +125C VCC 5V 10% 5V 10%
Electrical Characteristics Over the Operating Range[3,4]
Parameter VOH VOL VIH VIL IIX VCD IOZ IOS ICC VPP IPP VIHP VILP Description Output HIGH Voltage Output LOW Voltage Input HIGH Level Input LOW Level Input Leakage Current Input Clamp Diode Voltage Output Leakage Current Output Short Circuit Current Power Supply Current Programming Supply Voltage Programming Supply Current Input HIGH Programming Voltage Input LOW Programming Voltage 3.0 0.4 Test Conditions VCC = Min., IOH = -4.0 mA VIN = VIH or VIL VCC = Min., IOL = 16 mA VIN = VIH or VIL Guaranteed Input Logical HIGH Voltage for All Inputs Guaranteed Input Logical LOW Voltage for All Inputs GND < VIN < VCC Note 4 GND < VOUT < VCC, Output Disabled[5] VCC = Max., VOUT = IOUT = 0 mA VCC = Max. 0.0V[6] Commercial Military 12 -10 -20 +10 -90 90 120 13 50 V mA V V A mA mA -10 2.0 0.8 +10 Min. 2.4 0.4 Max. Unit V V V V A
Notes 1. The Voltage on any input or I/O pin cannot exceed the power pin during power-up. 2. TA is the "instant on" case temperature. 3. See the last page of this specification for Group A subgroup testing information. 4. See the "Introduction to CMOS PROMs" section of the Cypress Data Book for general information on testing. 5. For devices using the synchronous enable, the device must be clocked after applying these voltages to perform this measurement. 6. For test purposes, not more than one output at a time should be shorted. Short circuit test duration should not exceed 30 seconds.
Document #: 38-04001 Rev. *C
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CY7C225A
Capacitance[4]
Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC =5.0V Max. 10 10 Unit pF pF
AC Test Loads and Waveforms[4]
5V OUTPUT 50 pF INCLUDING JIG AND SCOPE R2 167 R1 250 5V OUTPUT 5pF INCLUDING JIG AND SCOPE R2 167 R1 250 ALL INPUT PULSES 3.0V GND < 5 ns 90% 10% 90% 10% < 5 ns
(a) NormalLoad
Equivalent to: THEVENIN EQUIVALENT OUTPUT 100
(b) High Z Load
2.0V
Operating Modes
The CY7C225A incorporates a D-type, master-slave register on chip, reducing the cost and size of pipelined microprogrammed systems and applications where accessed PROM data is stored temporarily in a register. Additional flexibility is provided with synchronous (ES) and asynchronous (E) output enables and CLEAR and PRESET inputs. Upon power-up, the synchronous enable (ES) flip-flop will be in the set condition causing the outputs (O0-O7) to be in the OFF or high-impedance state. Data is read by applying the memory location to the address inputs (A0-A8) and a logic LOW to the enable (ES) input. The stored data is accessed and loaded into the master flip-flops of the data register during the address set-up time. At the next LOW-to-HIGH transition of the clock (CP), data is transferred to the slave flip-flops, which drive the output buffers, and the accessed data will appear at the outputs (O0-O7) provided the asynchronous enable (E) is also LOW. The outputs may be disabled at any time by switching the asynchronous enable (E) to a logic HIGH, and may be returned to the active state by switching the enable to a logic LOW. Regardless of the condition of E, the outputs will go to the OFF or high-impedance state upon the next positive clock edge after the synchronous enable (ES) input is switched to a HIGH level. If the synchronous enable pin is switched to a logic LOW,
the subsequent positive clock edge will return the output to the active state if E is LOW. Following a positive clock edge, the address and synchronous enable inputs are free to change since no change in the output will occur until the next LOW-to-HIGH transition of the clock. This unique feature allows the CY7C225A decoders and sense amplifiers to access the next location while previously addressed data remains stable on the outputs. System timing is simplified in that the on-chip edge-triggered register allows the PROM clock to be derived directly from the system clock without introducing race conditions. The on-chip register timing requirements are similar to those of discrete registers available in the market. The CY7C225A has buffered asynchronous CLEAR and PRESET inputs. Applying a LOW to the PRESET input causes an immediate load of all ones into the master and slave flip-flops of the register, independent of all other inputs, including the clock (CP). Applying a LOW to the CLEAR input, resets the flip-flops to all zeros. The initialize data will appear at the device outputs after the outputs are enabled by bringing the asynchronous enable (E) LOW. When power is applied, the (internal) synchronous enable flip-flop will be in a state such that the outputs will be in the high-impedance state. In order to enable the outputs, a clock must occur and the ES input pin must be LOW at least a set-up time prior to the clock LOW-to-HIGH transition. The E input may then be used to enable the outputs.
Document #: 38-04001 Rev. *C
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CY7C225A
Switching Characteristics Over the Operating Range[3,4]
7C225A-25 Parameter tSA tHA tCO tPWC tSES tHES tDP, tDC tRP, tRC tPWP, tPWC tCOS tHZC tDOE tHZE Description Address Set-Up to Clock HIGH Address Hold from Clock HIGH Clock HIGH to Valid Output Clock Pulse Width ES Set-Up to Clock HIGH ES Hold from Clock HIGH Delay from PRESET or CLEAR to Valid Output PRESET or CLEAR Recovery to Clock HIGH PRESET or CLEAR Pulse Width Valid Output from Clock HIGH[7] Inactive Output from Clock HIGH[7] Valid Output from E LOW Inactive Output from E HIGH 15 15 20 20 20 20 10 10 0 20 20 20 20 20 20 20 Min. 25 0 12 15 10 5 20 20 20 30 30 30 30 Max. 7C225A-30 Min. 30 0 15 20 10 5 20 Max. 7C225A-40 Min. 40 0 25 Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns
Switching Waveforms[4]
tHA A0 - A10 tSES ES tSES tPWC tPWC tHES tPWC tPWC tPWC tPWC tHES tSES tHES tSA tHA
CP
O0 - O7 tCO tHZC
tCOS
tCO tHZE tDOE
E tDP tDC PS or CLR tPWP tPWC tRP tRC ,
Note 7. Applies only when the synchronous (ES) function is used.
Document #: 38-04001 Rev. *C
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CY7C225A
Programming Information
Programming support is available from Cypress as well as from a number of third-party software vendors. For detailed Table 1. Mode Selection
programming information, including a listing of software packages, please see the PROM Programming Information located at the end of this section. Programming algorithms can be obtained from any Cypress representative.
Pin Function[8] Read or Output Disable Mode Read Output Disable Output Disable Clear Preset Program Program Verify Program Inhibit Intelligent Program Blank Check Other A8-A0 A8-A0 A8-A0 A8-A0 A8-A0 A8-A0 A8-A0 A8-A0 A8-A0 A-A0 A8-A0 A8-A0 CP PGM X X X X X VILP VIHP VIHP VILP VIHP ES VFY VIL VIH X VIL VIL VIHP VILP VIHP VIHP VILP CLR VPP VIH VIH VIH VIL VIH VPP VPP VPP VPP VPP E E VIL X VIH VIL VIL VIHP VIHP VIHP VIHP VIHP PS PS VIH VIH VIH VIH VIL VIHP VIHP VIHP VIHP VIHP O7-O0 D7-D0 O7-O0 High Z High Z Zeros Ones D7-D0 O7-O0 High Z D7-D0 Zeros
Figure 1. Programming Pinouts
DIP Top View
A7 A6 A5 A4 A3 A2 A1 A0 D0 D1 D2 GND 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VCC A8 PS E VPP VFY PGM D7 D6 D5 D4 D3 A4 A3 A2 A1 A0 NC D0
LCC/PLCC Top View
A5 A6 A7 NC V CC A8 PS 4 3 2 1 28 27 26 25 5 24 6 23 7 22 8 21 9 20 10 19 11 12 1314151617 18 D1 D2 GND NC D3 D4 D5 E VPP VFY PGM NC D7 D6
Note 8. X = "don't care" but not to exceed VCC 5%.
Document #: 38-04001 Rev. *C
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CY7C225A
Typical DC and AC Characteristics
NORMALIZED SUPPLY CURRENT vs. SUPPLY VOLTAGE
1.6 NORMALIZED I CC 1.4 1.2 1.0 0.8 0.6 4.0 TA =25C f = fMAX 4.5 5.0 5.5 6.0 1.2
NORMALIZEDOCK- CL TO-OUTPUT TIME
NORMALIZED SUPPLY CURRENT vs. AMBIENT TEMPERATURE
CLOCK TO OUTPUT TIME vs. VCC
1.6 1.4 1.2 1.0 0.8 TA =25C 0.6 4.0 4.5 5.0 5.5 6.0
NORMALIZED ICC
1.1
1.0
0.9
0.8 -55
25
125
SUPPLY VOLTAGE (V)
AMBIENT TEMPERATURE (C)
SUPPLY VOLTAGE (V)
NORMALIZED CLOCK- TO-OUTPUT TIME
CLOCK TO OUTPUT TIME vs. TEMPERATURE
1.6 NORMALIZED SET-UP TIME 1.4 1.2 1.0 0.8 0.6 -55 1.2
NORMALIZED SET-UP TIME vs. SUPPLY VOLTAGE
1.6 NORMALIZED SET -UP TA =25C 0.4 4.0 4.5 5.0 5.5 6.0 1.4 1.2 1.0 0.8 0.6 -55
NORMALIZED SET-UP TIME vs. TEMPERATURE
1.0
0.8
0.6
25
125
25
125
AMBIENT TEMPERATURE (C)
SUPPLY VOLTAGE (V)
AMBIENT TEMPERATURE (C)
OUTPUT SINK CURRENT (mA)
NORMALIZED SUPPLY CURRENT vs. CLOCK PERIOD
1.02 1.00 NORMALIZED ICC 0.98 0.96 0.94 0.92 0.90 0.88 0 25 50 75 100 VCC =5.5V TA =25C 30.0 25.0 DELTA t AA (ns) 20.0 15.0 10.0 5.0 0.0
TYPICAL ACCESS TIME CHANGE vs. OUTPUT LOADING
OUTPUT SINK CURRENT vs. OUTPUT VOLTAGE
175 150 125 100 75 50 25 0 0.0 1.0 2.0 3.0 4.0 VCC =5.0V TA =25C
TA =25C VCC =4.5V 0 200 400 600 800 1000
CLOCK PERIOD (ns)
CAPACITANCE (pF)
OUTPUT VOLTAGE (V)
Document #: 38-04001 Rev. *C
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CY7C225A
Ordering Information
Speed (ns) tSA 25 tCO 12 Ordering Code CY7C225A-25PC Package Type P13 Package Type 24-Lead (300-Mil) Molded DIP Operating Range Commercial
MILITARY SPECIFICATIONS Group A Subgroup Testing DC Characteristics
Parameter VOH VOL VIH VIL IIX IOZ ICC Subgroups 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3
Switching Characteristics
Parameter tSA tHA tCO tDP tRP Subgroups 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11
Package Diagrams
Figure 2. 28-Lead Plastic Leaded Chip Carrier J64
51-85001-*A
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CY7C225A
Package Diagrams (Continued)
Figure 3. 28-Square Leadless Chip Carrier L64
MIL-STD-1835 C-4
51-80051-**
Document #: 38-04001 Rev. *C
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CY7C225A
Package Diagrams (Continued)
Figure 4. 24-Lead (300-Mil) PDIP P13
51-85013-*B
All product and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-04001 Rev. *C
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(c) Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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CY7C225A
Document History Page
Document Title: CY7C225A 512 x 8 Registered PROM Document Number: 38-04001 REV. ** *A *B *C ECN NO. 113858 118892 122242 499538 Issue Date 03/06/02 10/09/02 12/27/02 See ECN Orig. of Change DSG GBI RBI PCI Description of Change Changed from Spec number: 38-00228 to 38-04001 Updated ordering information Added power up requirements to Maximum Ratings Information Updated ordering information
Document #: 38-04001 Rev. *C
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